1. Field of the Invention
The invention relates to a method of fabricating a gate of a semiconductor device, and more particularly, to a method of forming a dual gate.
2. Description of the Related Art
As semiconductor fabrication has reached the deep sub-micron stage, gates need to be formed with increasingly smaller dimensions, and with increasingly faster operation speed. The operation voltage is thus lowered, and consequently a change in material and fabrication must be made to avoid any device instability.
Conventionally, in either an N-channel metal-oxide semiconductor (NMOS) or a P-channel metal-oxide semiconductor (PMOS), a gate is formed of a polysilicon layer doped with N-type ions. A tungsten silicide layer and a silicon nitride layer are then formed on the gate. While forming a PMOS, an ion implantation is performed to an N-well or an N-type substrate for adjusting the threshold voltage of the PMOS. As a consequence, a PN junction is formed to induce a depletion region. The induced depletion region induces an equivalent buried channel device that causes a short channel effect, so that problems arise, such as sub-threshold voltage and an inability of the gate to control the device.
Due to the above problems, a method of doping P-type ions into a polysilicon gate of a PMOS has been developed. Thus, a complementary MOS (CMOS) comprising two gates doped with different conductive types has been formed and has become a leading trend for further development of gate fabrication. For example, embedded dynamic random access memory (Embedded DRAM) employs this type of gate.
FIG. 1A to FIG. 1D show a conventional method of fabricating a dual gate. In FIG. 1A, a substrate 100 is provided. Using ion implantation, an N-well 101 and a P-well 102 are formed in the substrate 100. A shallow trench isolation 103 is formed between the N-well 101 and P-well 102 for isolation. A gate oxide layer 104 is formed on the substrate 100. A polysilicon layer 105 is formed on the gate oxide layer 104. The part of the polysilicon layer 105 over the P-well 102 is covered by a photoresist layer 106, while the other part polysilicon layer 105 over the N-well 101 is exposed. N-type ions are implanted into the exposed part of the polysilicon layer 105.
In FIG. 1B, the photoresist layer 106 is removed. Another photoresist layer 107 is formed to cover the part of the polysilicon layer 105 over the N-well 101, and the polysilicon layer 105 over the P-well 102 is exposed. P-type ions are implanted into the exposed part of the polysilicon layer 105.
In FIG. 1C, the photoresist layer 107 is removed. A high temperature diffusion is performed to define the N-type polysilicon layer 105a on the N-well 101 and the P-type polysilicon layer 105b on the P-well 102. A part of the N-type polysilicon layer 105a and a part of the P-type polysilicon layer 105b are removed to form an N-type gate 105a on the N-well 101 and a P-type gate 105b on the P-well 102. Spacers 109 are formed on the sidewalls of the N-type gate 105a and on the P-type gate 105b. Source/drain regions 111a and 111b are formed in the in the substrate beside the N-type gate 105a and the P-type gate 105b, respectively.
In FIG. 1D, a titanium layer (not shown) is formed on the N-type gate 105a and the P-type gate 105b. A thermal process is performed to form self-aligned silicide on the N-type gate 105a, the P-type gate 105b and the source/drain regions 111a, 111b. The remaining titanium layer is removed.
Since the silicide 113 is formed from titanium and doped polysilicon, the silicide 113 has a high resistance. To decrease the resistance of the silicide, dopant concentration in the polysilicon is limited. However, a doping concentration of the N-type polysilicon and a doping concentration of the P-type polysilicon are lower, and the area of a depletion region between the P-type polysilicon and the N-type polysilicon is larger.